Senior AI Modeling Architect
- Hod Hasharon
- Drushim
- Verified live ·
Description
We are looking for a Senior AI Modeling Architect to define and model the architecture of our next-generation AI processors. In this role, you will serve as a key technical authority — bringing not only strong modeling capabilities, but also the architectural vision to propose and drive end-to-end solutions to complex design challenges. You will work at high levels of abstraction, partnering closely with HW and SW architects to co-invent optimal solutions, validate them through simulation, and influence design decisions based on experimental data. • B.Sc. or higher in Electrical Engineering, Computer Science, or related discipline • 10+ years of experience in VLSI/processor architecture (exceptional candidates with less experience will be considered) • Strong hands-on experience with SystemC modeling • Solid background in AI workloads and AI hardware architecture • Experience in HW/SW co-design and architectural trade-off analysis • Ability to operate at high levels of abstraction and drive architectural decisions from simulation data Responsibilities • Model CPU/AI processor functionality and performance using SystemC and pre-silicon simulation environments • Define and drive architectural solutions — not only identify problems, but come with concrete proposals and alternatives • Partner with lead HW and SW architects to co-design features and evaluate trade-offs across the stack • Analyze bottlenecks and performance on workloads reflecting future AI use cases • Provide proof-of-concept implementations for new architectural features and design alternatives • Potentially lead feature definition in addition to the modeling role Skills • Strong independent technical judgment — able to come with a solution, not just a model • Excellent interpersonal and collaboration skills • Creative, self-driven, and a strong team player Advantages • Experience in CPU/DSP/GPU processor core architecture definition • Familiarity with AI accelerator design and large-scale inference solutions • Exposure to ISA definition or new instruction design