SoC and IP Design Engineer, Networking

Minimum qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience. 8 years of experience in digital logic design and RTL development using Verilog or SystemVerilog. Experience with IP integration, subsystem design, or System-on-Chip (SoC) architecture. Experience with logic synthesis, timing closure, and low-power design techniques. Experience with RTL quality and sign-off tools (e.g., Lint, CDC).