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Package Design/Technology/Layout Engineer

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  • Cadence / Synopsys EDA

Description

Minimum qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 1 year of experience with semiconductor package design and substrate layout. Experience with industry-standard packaging EDA tools such as Cadence APD/APD+, Cadence Allegro, or Siemens/Mentor Xpedition.

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