Senior ASIC Logic Design Engineer for Wireless SoC Group

Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance of every detail? Come join Apple’s growing wireless silicon development team! As part of our Silicon Technologies group, you’ll help design our next-generation, power-efficient, system-on-chip (SoC). Our wireless SoC organization is responsible for all aspects of wireless silicon development. With a particular emphasis on highly energy-efficient design and new technologies that transform the user experience at the product level. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices. If you enjoy a fast-paced and challenging environment, and collaborating with people across different functional areas as well as thriving during crisis times, we encourage you to apply. - Responsibility of block and/or sub-system micro-architecture and design implementation - Work with architects and system teams to define the right solution for the product requirements - Implement block and/or sub-system design, analyze performance and power and support verification teams - Responsible for FE flows such as synthesis, CDC, RDC and Lint to ensure high-quality, production-worthy design - Collaborate with cross-functional teams across geographies to align on technical direction and resolve integration challenges - Mentor junior engineers and contribute to design methodology improvements Minimum qualifications: B.Sc. in Electrical Engineering or Computer Engineering, or related fields 10+ years of hands-on experience in ASIC design flow Preferred qualifications: Solid background in design micro-architecture Experience in ASIC design front end flows, such as Lint, CDC, RDC Experience in bus-fabrics and low power design is a plus Self-starter, highly motivated, highly organized, and schedule-driven Extensive hands-on experience with low power design techniques including multiple power domains, voltage/frequency scaling, power gating, and retention strategies Deep knowledge of AMBA protocols (AXI, AHB, APB) and complex on-chip interconnect/fabric architectures