Senior Technical Program Manager, Chip DevOps and Methodology

Minimum qualifications Bachelor's degree in Engineering, Computer Science, or equivalent practical experience. 8 years of experience as a technical program manager or engineering lead. Experience in supporting unified design/verification methodologies (e.g., standardized UVM frameworks, unified linting/CDC rules, automated regression tracking) or experience with software engineering lifecycle management or Site Reliability Engineering (SRE) principles. Experience with the front-to-back silicon design lifecycle (e.g., RTL design, verification, synthesis, STA, place and route, tape-out) or experience in building automation, CI/CD pipelines, and Infrastructure as Code (IaC) environments for engineering workflows.