VLSI VERIFICATION ENGINEER

Responsibilities Develop, debug, and maintain verification environments and testbenches using SystemVerilog and UVM. Analyze simulation results and waveforms to identify, isolate, and root-cause bugs in design or testbench code. Define, track, and analyze code and functional coverage metrics, and drive coverage closure on assigned blocks. Own the verification of assigned IP blocks or features end-to-end, from test planning through sign-off. Collaborate with the design team to clarify specifications and confirm verification completeness. For additional details and the most recent updates, hit “Apply for job” Show more Show less